Description

Reconfigurable digital hardware platforms such as field programmable gate arrays (FPGAs) can provide added advantages over real-time implementation of digital signal processing (DSP) algorithms via massive hardware level parallelism. Such hardware implementation of DSP algorithms typically requires mapping of a mathematical description of an algorithm to a suitable hardware implementation architecture, while taking into account speed, throughput and computational complexity constraints. This talk will discuss some of the commonly used design techniques to obtain hardware-friendly implementation architectures of simple DSP algorithms such as FIR/IIR filters. In particular, the talk will go through design concepts such as pipelining and parallel processing and provide some examples from FPGA implementation of simple DSP systems.