VLSI Workshop by Synopsis
January 20, 2024 · 3:00 AM - 10:30 AM @ Department of Computer Engineering, Peradeniya, Faculty of Engineering
Description
The VLSI Workshop by Synopsys is an essential part of the practical learning experience for students pursuing the VLSI Design course, providing hands-on exposure to the industry-standard tools and methodologies used in the semiconductor design process. The workshop covers topics like digital design flow, RTL (Register Transfer Level) synthesis, verification techniques, and physical design implementation, providing students with a comprehensive understanding of the VLSI design cycle. It is especially valuable for students aiming to work in the semiconductor industry, giving them real-world experience with tools used in designing and testing integrated circuits (ICs) on a large scale. The workshop concluded successfully with students gaining practical insights into Synopsys' software tools, such as Design Compiler and IC Compiler. Participants were guided through the design flow starting from high-level design entry using hardware description languages (HDL) to the synthesis of these designs into gate-level implementations. The interactive tutorial sessions, led by experts from Synopsys, helped students work on real-time design challenges and understand optimization techniques for improving performance and power efficiency in VLSI systems. The workshop was an enriching experience, bridging the gap between academic concepts and industry practices.
Agenda
08:30 AM - Welcome speech by Dr.Isuru Dassanayake 09:00 AM - Session 1 10:30 AM - Refreshments 11:00 AM - Session 1 continuation 12:00 PM - Lunch time 1:00 PM - Session 2 3:00 PM - Refreshments 3:30 PM - Session 2 Continuation 4:00 PM - End of the program