VLSI Workshop 1 by Synopsys
February 1, 2025 · 3:00 AM - 10:30 AM @ Computer Lab 02, Peradeniya, Faculty of Engineering
Description
The VLSI Workshop conducted by Synopsys successfully provided students with hands-on exposure to advanced Electronic Design Automation (EDA) tools, bridging the gap between theoretical learning and practical applications in VLSI design and verification . The workshop was effectively executed with a structured approach, starting with an introduction to modern semiconductor workflows and progressing to in-depth sessions on industry-standard tools such as VC Spyglass for static verification, VCS for functional verification, and Design Compiler for logic synthesis. Interactive demonstrations and guided explanations ensured participants could directly relate tool usage to real-world design scenarios. This initiative embodied IEEE’s mission of advancing technology for humanity by empowering students with relevant technical knowledge. It also promoted collaboration, lifelong learning, and professional growth , aligning with IEEE’s commitment to developing future-ready engineers. This impactful workshop set a strong foundation for students aspiring to excel in semiconductor design and verification . Impact: Enhanced participants’ understanding of EDA toolchains and their relevance in the semiconductor industry. Inspired undergraduates to explore career opportunities and research in VLSI and digital design domains. Strengthened collaboration between academia and industry by enabling direct interaction with experts.
Agenda
Welcome Speech by Dr. Isuru Dassanayake 08:30 AM – 09:00 AM Session 1 09:00 AM – 10:30 AM Refreshments 10:30 AM – 11:00 AM Session 1 – Continuation 11:00 AM – 12:00 PM Lunch Break 12:00 PM – 01:00 PM Session 2 01:00 PM – 03:00 PM Refreshments 03:00 PM – 03:30 PM Session 2 – Continuation 03:30 PM – 04:00 PM